Difference between revisions of "FPGA Transmitter"

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== (001) Transmit "I" ==
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== (101) Transmit "S" ==
  
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This is a simple state.  It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (any value) in all remaining bytes (minimum size of data is 46 bytes, so there needs to be 45 bytes of padding).  After the transmission is complete, the block writes a 010 to the state register.
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This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it.  Once the packet has been sent, the block transitions to state 010.
  
 
inputs
 
inputs
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internal signals
 
internal signals
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* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
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* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
 
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
 
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
  
 
blocks
 
blocks
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* '''Transmitter'''
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* '''Temp Loader'''
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** Loads an ASCII "I" (0x49, 0100 1001) to the transmitter 46 times (the first value must be "I" and the rest are garbage, so padding with "I" is simplest) to fill in a complete packet (accounts for any register incrementing or other loading control necessary).
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** This block reads the temperature value from the internal registers and loads it to the transmit buffer.
 
** inputs
 
** inputs
 
*** ''Clk'': clock
 
*** ''Clk'': clock
 
*** ''/Rst'': asynchronous, active-low reset
 
*** ''/Rst'': asynchronous, active-low reset
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*** ''Go'': pulse to begin sending
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*** ''Go'': pulse to begin; feeds from ''Go'' internal signal of block 101
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*** ''Inc'': ''Done'' signal from transceiver; initiates next sending
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*** ''D_in'': 16-bit data bus from internal registers
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*** ''TxRx_Done'': ''Done'' signal from transceiver
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** ouputs
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*** ''TxRx_Go'': ''Go'' signal on transceiver
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*** ''TxRx_R/W'': ''R/W'' signal on transceiver
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*** ''TxRx_A'': ''A_in'' bus on transceiver
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*** ''TxRx_D'': ''D_in'' bus on transceiver
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*** ''Done'': pulse to signal completion
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* '''ADC Loader'''
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** This block reads the ADC values from the internal registers and loads them to the transmit buffer in order: channel zero to channel seven.
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** inputs
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*** ''Clk'': clock
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*** ''/Rst'': asynchronous, active-low reset
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*** ''Go'': pulse to begin; feeds from ''Done'' signal of Temp Loader
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*** ''D_in'': 16-bit data bus from internal registers
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*** ''TxRx_Done'': ''Done'' signal from transceiver
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** ouputs
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*** ''Sel'': 3-bit select bus for internal registers
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*** ''TxRx_Go'': ''Go'' signal on transceiver
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*** ''TxRx_R/W'': ''R/W'' signal on transceiver
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*** ''TxRx_A'': ''A_in'' bus on transceiver
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*** ''TxRx_D'': ''D_in'' bus on transceiver
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*** ''Done'': pulse to signal completion
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* '''Padder'''
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** This block pads the packet to the minimum 46 bytes.  Only 19 bytes have been loaded by this point (1 byte "S", 2 byte temperature, 8 x 2 byte ADC), so 27 bytes of padding (zero) must be loaded.
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** inputs
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*** ''Clk'': clock
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*** ''/Rst'': asynchronous, active-low reset
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*** ''Go'': pulse to begin; feeds from ''Done'' signal of ADC Loader
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*** ''TxRx_Done'': ''Done'' signal from transceiver
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** outputs
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*** ''TxRx_Go'': ''Go'' signal on transceiver
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*** ''TxRx_R/W'': ''R/W'' signal on transceiver
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*** ''TxRx_A'': ''A_in'' bus on transceiver
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*** ''TxRx_D'': ''D_in'' bus on transceiver
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*** ''Done'': pulse to signal completion
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* '''Sender'''
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** This block tells the CP2200/1 to send the completed packet.
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** inputs
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*** ''Clk'': clock
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*** ''/Rst'': asynchronous, active-low reset
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*** ''Go'': pulse to begin; feeds from ''Done'' signal of Padder
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*** ''TxRx_Done'': ''Done'' signal from transceiver
 
** outputs
 
** outputs
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*** ''TxRx_A'': ''A_in'' signal to transceiver
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*** ''TxRx_Go'': ''Go'' signal on transceiver
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*** ''TxRx_D'': ''D_in'' signal to transceiver
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*** ''TxRx_R/W'': ''R/W'' signal on transceiver
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*** ''TxRx_R/W'': ''R/W'' signal to transceiver; tied to write (zero)
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*** ''TxRx_A'': ''A_in'' bus on transceiver
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*** ''TxRx_Go'': ''Go'' signal to transceiver
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*** ''TxRx_D'': ''D_in'' bus on transceiver
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*** ''Done'': pulses for one cycle; connects to state register as an enable line
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*** ''Done'': pulse to signal completion
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*** ''New_St'': new state to load into state register; goes to 010 when ''Done'' is high
 

Revision as of 19:03, 16 May 2008

(101) Transmit "S"

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.

inputs

  • Clk: clock
  • /Rst: asynchronous, active-low reset
  • State: 3-bit state value

internal signals

  • S_En: state enable, S_En <= not (St(2) or St(1) or St(0))
  • Go: when S_En goes high Go pulses for one cycle

blocks

  • Temp Loader
    • This block reads the temperature value from the internal registers and loads it to the transmit buffer.
    • inputs
      • Clk: clock
      • /Rst: asynchronous, active-low reset
      • Go: pulse to begin; feeds from Go internal signal of block 101
      • D_in: 16-bit data bus from internal registers
      • TxRx_Done: Done signal from transceiver
    • ouputs
      • TxRx_Go: Go signal on transceiver
      • TxRx_R/W: R/W signal on transceiver
      • TxRx_A: A_in bus on transceiver
      • TxRx_D: D_in bus on transceiver
      • Done: pulse to signal completion
  • ADC Loader
    • This block reads the ADC values from the internal registers and loads them to the transmit buffer in order: channel zero to channel seven.
    • inputs
      • Clk: clock
      • /Rst: asynchronous, active-low reset
      • Go: pulse to begin; feeds from Done signal of Temp Loader
      • D_in: 16-bit data bus from internal registers
      • TxRx_Done: Done signal from transceiver
    • ouputs
      • Sel: 3-bit select bus for internal registers
      • TxRx_Go: Go signal on transceiver
      • TxRx_R/W: R/W signal on transceiver
      • TxRx_A: A_in bus on transceiver
      • TxRx_D: D_in bus on transceiver
      • Done: pulse to signal completion
  • Padder
    • This block pads the packet to the minimum 46 bytes. Only 19 bytes have been loaded by this point (1 byte "S", 2 byte temperature, 8 x 2 byte ADC), so 27 bytes of padding (zero) must be loaded.
    • inputs
      • Clk: clock
      • /Rst: asynchronous, active-low reset
      • Go: pulse to begin; feeds from Done signal of ADC Loader
      • TxRx_Done: Done signal from transceiver
    • outputs
      • TxRx_Go: Go signal on transceiver
      • TxRx_R/W: R/W signal on transceiver
      • TxRx_A: A_in bus on transceiver
      • TxRx_D: D_in bus on transceiver
      • Done: pulse to signal completion
  • Sender
    • This block tells the CP2200/1 to send the completed packet.
    • inputs
      • Clk: clock
      • /Rst: asynchronous, active-low reset
      • Go: pulse to begin; feeds from Done signal of Padder
      • TxRx_Done: Done signal from transceiver
    • outputs
      • TxRx_Go: Go signal on transceiver
      • TxRx_R/W: R/W signal on transceiver
      • TxRx_A: A_in bus on transceiver
      • TxRx_D: D_in bus on transceiver
      • Done: pulse to signal completion
Retrieved from "https://zeus.phys.uconn.edu/wiki/index.php?title=FPGA_Transmitter&oldid=3491"