Digital control board documentation

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

Power Requirements

Required Voltages

All components on the digital board except the DAC can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see Setting the Output Range). Digital and analog grounds must be connected as well before any testing takes place.

Power Pins

Power shall be connected to the board as follows:

Voltage	Eurocard Pin
DGND	A6
AGND	A5
+5V	A4
-5V	A3
High voltage (DAC max out +10)	A2

Power Supply Sequencing

The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

1. Ensure AGND/DGND are connected/grounded
2. +5V
3. -5V
4. High voltage

FPGA

The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

Power Details

The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

Logic Standard

The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a 3.3V CMOS logic standard.

Pinout Table

Pin #	Net Name	Signal Name	Description
P1	FPGA/TMS	[JTAG]	JTAG
P2	FPGA/TDI	[JTAG]	JTAG
P3	AD7928/CS	SPI_A_iCS	SPI chip select for ADC
P4	SPI	SPI_SDO	Erroneously wired SPI bus trace Now connects to SDO on temp. sensor and on ADC
P5	CLK_5MHZ	SPI_SCLK	5 MHz clock output for SPI bus (ADC and temp. sensor)
P6	No connection
P7	No connection
P8	DGND
P9	No connection
P10	No connection
P11	+3.3V
P12	No connection
P13	No connection
P14	DGND
P15	No connection
P16	No connection
P17	+1.2V
P18	DGND
P19	dBinfo_Start
P20	dBinfo_Stream
P21	No connection
P22	+3.3V
P23	DGND	[M1: JTAG prog. config.]
P24	DGND	[M2: JTAG prog. config.]
P25	DGND	[M0: JTAG prog. config.]
P26	+3.3V
P27	FPGA/CLK_IN	fClk	20 MHz clock input from crystal oscillator
P28	No connection
P29	No connection	(db) state_Q(0)
P30	No connection
P31	No connection	(db) state_Q(1)
P32	No connection
P33	No connection	(db) state_Q(2)
P34	No connection
P35	CP2201/INT	Eth_iINT	Ethernet controller interrupt
P36	MASTER_RESET	Rst	Connects to RESET jumper in upper left of board (active-low, externally pulled up)
P37	(manually wired)	fClk_out
P38	+1.2V
P39	No connection
P40	CP2201/CS	iCS	Chip select for ethernet controller
P41	CP2201/WR	iWR	Write enable for ethernet controller
P42	DGND
P43	CP2201/RD	iRD	Read enable for ethernet controller
P44	CP2201/ALE	ALE	Address line enable for ethernet controller
P45	+3.3V
P46	CP2201/RESET	Eth_iRst	Reset pin for ethernet controller
P47	DGND
P48	FPGA/INIT_B	[JTAG]	Used during FPGA configuration - see Xilinx documentation
P49	CP2201/AD0	AD(0)	Ethernet controller address/data bus, bit 0
P50	CP2201/AD1	AD(1)	Ethernet controller address/data bus, bit 1
P51	FPGA/DIN	[JTAG]	Serial data input from EEPROM for configuration
P52	CP2201/AD2	AD(2)	Ethernet controller address/data bus, bit 2
P53	FPGA/CCLK	[JTAG]	Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
P54	FPGA/DONE	[JTAG]	Gives configuration status - see Xilinx documentation
P55	+3.3V
P56	CP2201/AD3	AD(3)	Ethernet controller address/data bus, bit 3
P57	CP2201/AD4	AD(4)	Ethernet controller address/data bus, bit 4
P58	DGND
P59	CP2201/AD5	AD(5)	Ethernet controller address/data bus, bit 5
P60	CP2201/AD6	AD(6)	Ethernet controller address/date bus, bit 6
P61	CP2201/AD7	AD(7)	Ethernet controller address/date bus, bit 7
P62	No connection
P63	DGND
P64	No connection
P65	No connection
P66	+1.2V
P67	+3.3V
P68	+3.3V
P69	DGND
P70	ID3	LocStamp(3)	Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
P71	ID2	LocStamp(2)	Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
P72	ID1	LocStamp(1)	Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
P73	ID0	LocStamp(0)	Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
P74	DGND
P75	FPGA/TDO	[JTAG]	JTAG
P76	FPGA/TCK	[JTAG]	JTAG
P77	ID4	LocStamp(4)	Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
P78	No connection
P79	+3.3V
P80	DGND
P81	+1.2V
P82	No connection	(db) dbShort	Shorts out the waiting timer in FPGA for Ethernet controller initialization (pulled low)
P83	CLK_5MHZ_2	DAC_Clk	5 MHz clock output for DAC
P84	No connection
P85	AD5535/DIN	DAC_serData	DAC serial data input (FPGA out -> DAC in)
P86	No connection
P87	DGND
P88	AD5535/SYNC	DAC_setISync
P89	No connection
P90	No connection
P91	DGND
P92	+3.3V
P93	AD7314/CE	SPI_TCE	Chip enable for temperature sensor
P94	No connection
P95	DGND
P96	+3.3V
P97	(former AD7928/DOUT)		Erroneously wired ADC SPI bus connection Connects to DOUT on ADC
P98	AD5535/RESET	DAC_iRst	Reset pin for DAC
P99	DGND		PUDC_B pin - enables pullup resistors on user IO and input-only pins during FPGA config.
P100	FPGA/PROG_B	[JTAG]	Used during FPGA configuration - see Xilinx documentation

EEPROM

To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

Power Details

The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

Flashing/Burning/Writing

Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

FPGA Configuration

The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

Pinout Table

Pin #	Net Name	Description
1	FPGA/DIN	Serial data line Carries data from the EEPROM to the FPGA
2	No connection
3	FPGA/CCLK	Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
4	EEPROM/TDI	This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
5	FPGA/TMS	JTAG TMS Connects to both FPGA and EEPROM
6	FPGA/TCK	JTAG TCK Connects to both FPGA and EEPROM
7	FPGA/PROG_B	Used during configuration See Xilinx documentation
8	FPGA/INIT_B	Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
9	No connection
10	FPGA/DONE	Indicates completion of FPGA configuration High when complete
11	DGND
12-16	No connection
17	FPGA/TDI	This is the EEPROM's TDO/FPGA's TDI
18-20	+3.3V

JTAG Header

To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

Header Location and Size

The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

Power Details

The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

Pinout Table

Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Improper wiring will certainly cause undesired operation, and may cause damage as well. Damage is most likely to occur if one of the flying leads is improperly connected to an odd numbered pin, since it will short to the PCB's ground plane.

Pin #	Net Name	Flying Lead	Description
1, 3, 5, 7, 9, 11, 13 (odd pins)	DGND	Black (connect to any odd numbered pin)	Ground pins for signal integrity Never connect a flying lead other than the black lead to an odd numbered pin Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
2	+3.3V	Red/VREF	Power source for all JTAG logic
4	FPGA/TMS	Green/TMS	JTAG TMS - connects to EEPROM and FPGA
6	FPGA/TCK	Yellow/TCK	JTAG TCK - connects to EEPROM and FPGA
8	FPGA/TDO	Purple/TDO	JTAG boundary scan chain endpoint
10	EEPROM/TDI	White/TDI	JTAG boundary scan chain start point
12	No connection		Pin is floating
14	No connection		Pin is floating

The gray HALT flying lead is not connected.

JTAG Overview

The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

DAC

The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

Power Details

The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in Power Requirements. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

Setting the Output Range

The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

• Max output voltage = VREF*50
• Minimum high voltage supply = VREF*50 + 10
• Acceptable range for VREF
  • Min: 1V
  • Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

Thermal Diode

The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

Pinout Table

See documentation from Analog Devices.

Channel Mapping

Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

DAC Channel #	DAC Pin #	Digital Board Eurocard Pin #	Amplifier Board Eurocard Pin #	Amplifier Channel #
0	B1	B3	B6	6
1	A2	C4	B7	7
2	D1	B2	B4	4
3	C2	C3	B5	5
4	B3	B4	B8	8
5	E2	C2	B3	3
6	F3	B1	B2	2
7	A4	B5	B10	10
8	E4	C5	B9	9
9	B5	C6	B11	11
10	F5	C1	B1	1
11	A6	C7	B13	13
12	E6	B6	B12	12
13	B7	B7	B14	14
14	F7	C10	B19	19
15	E8	C8	B15	15
16	A8	B8	B16	16
17	B9	C9	B17	17
18	F9	C16	B31	GAINMODE
19	E10	B11	B22	22
20	A10	B9	B18	18
21	B11	B10	B20	20
22	C12	B12	B24	24
23	D13	B13	B26	26
24	E12	B14	B28	28
25	A12	C11	B21	21
26	B13	C12	B23	23
27	H13	B16	Not connected	No amplifier connection
28	G14	B15	B30	30
29	C14	C13	B25	25
30	F13	C15	B29	29
31	E14	C14	B27	27 DACHEALTH See ADC Channel Descriptions.

ADC

The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

Power Details

The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

Setting the Measuring Range

The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

Data Interfacing

The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

Channel Descriptions

This table shows what signals are monitored by the ADC.

ADC Channel #	ADC Pin #	Net Name	Description
VIN0	16	AD7928/VHEALTH	This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
VIN1	15	AD5535/CATHODE	This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
VIN2	14	+3.3V	This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
VIN3	13	+5V	This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
VIN4	12	ADC_EXT1	This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
VIN5	11	+1.2V	This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
VIN6	10	ADC_EXT2	This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
VIN7	9	DACHEALTH	This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.

Pinout Table

Pin #	Net Name	Description
1	CLK_5MHZ	SPI clock (SCLK), from FPGA Shared with temperature sensor
2	DIN	SPI data in, from FPGA Shared with temperature sensor Currently wired wrong
3	CS	SPI chip select
4	AGND
5	+5V	Power pin
6	+5V	Power pin
7	AD7928/REF_IN	+2.5V reference, set by VR2
8	AGND
9-16	VIN[7:0]	See ADC Channel Descriptions
17	AGND
18	DOUT	SPI data out Currently wired incorrectly
19	+3.3V	VDRIVE, powers the SPI logic
20	AGND

Ethernet Controller

The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

Power Details

The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

Ethernet Jack

To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

Ethernet Jack Pins

These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).

• Pin 1: TX+
• Pin 2: AC coupled to DGND
• Pin 3: TX-
• Pin 4: RX+
• Pin 5: AC coupled to DGND
• Pin 6: RX-
• Pin 7: No connection
• Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress on the solder points when an ethernet wire is inserted or removed from the jack.

Crystal Oscillator

The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

Bus Format and Multiplexing

The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

Pinout Table

Pin #	Net Name	Description
1	CP2201/LA	Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
2	DGND	By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
3	+3.3V	AV+ power pin
4	CP2201/RX-	Connects to RX- on ethernet jack
5	CP2201/RX+	Connects to RX+ on ethernet jack
6	CP2201/TX+	Connects to TX+ on ethernet jack
7	CP2201/TX-	Connects to TX- on ethernet jack
8	+3.3V	"VDD" power pin
9	DGND	"DGND1" per the data sheet
10	CP2201/RESET	"RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
11-18	CP2201/AD[0:7]	Bits 0-7 of the address/data bus Connect to FPGA
19	+3.3V	"VDD" power pin
20	DGND	"DGND2" per the data sheet
21	CP2201/ALE	Address line enable Connects to FPGA See CP2201 documentation
22	CP2201/RD	Read strobe for AD bus Connects to FPGA See CP2201 documentation
23	CP2201/WR	Write strobe for AD bus Connects to FPGA See CP2201 documentation
24	CP2201/CS	Chip select Connects to FPGA
25	CP2201/INT	Interrupt request Connects to FPGA
26	DGND	"MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
27	CP2201/XTAL2	Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
28	FPGA/CLK_IN	"XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
29*	DGND	This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief

Eurocard Connector

At the bottom of the control board is the Eurocard connector, labelled P2. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in DAC Channel Mapping. Here is a table describing the purpose of pins in row A:

Row A Pinout Table

Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

Pin #	Net Name	Description
A1	CP2201/LA	Ethernet link/activity indicator routed to backplane
A2	High voltage input (+210V max)	High voltage input for DAC. See DAC for information about what voltage to input here.
A3	-5V	For DAC
A4	+5V	Powers most things on the board
A5	AGND
A6	DGND
A7	ADC_EXT1	Connects to ADC to monitor voltages on amplifier board See ADC
A8	ADC_EXT2	Connects to ADC to monitor voltages on amplifier board See ADC
A9	No connection
A10	No connection
A11	No conneciton
A12	ID4	Location identifier bit 4 Used to identify which backplane board is connected to See FPGA
A13	ID3	Location identifier bit 3 Used to identify which backplane board is connected to See FPGA
A14	ID2	Location identifier bit 2 Used to identify which backplane board is connected to See FPGA
A15	ID1	Location identifier bit 1 Used to identify which backplane board is connected to See FPGA
A16	ID0	Location identifier bit 0 Used to identify which backplane board is connected to See FPGA