Difference between revisions of "FPGA Reset"
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| − | + | :''See also [[Programming_the_Ethernet_controller|Programming the Ethernet Controller]]'' for a survey of modules and a general discussion of FPGA design approach.'' | |
| + | |||
| + | = (00X) Reset Modules = | ||
The reset modules Reset_hard (000) and Reset_soft (001) coordinate various stages of the board reset. The former, analogous to the cold boot of a computer, performs the basic initial reset steps dealing mainly with the startup and configuration of the Ethernet Controller chip (EC). The latter module is a more customized second stage of full reset or just a soft reset that concerns the sensor and DAC chips. It also records the MAC address of the tagger-controlling PC for further communication. (This cannot be handled in the Reset_hard stage as all registers on the EC and FPGA are cleared and the PC's MAC address stamped on the hard reset packet (R-packet) cannot be saved) | The reset modules Reset_hard (000) and Reset_soft (001) coordinate various stages of the board reset. The former, analogous to the cold boot of a computer, performs the basic initial reset steps dealing mainly with the startup and configuration of the Ethernet Controller chip (EC). The latter module is a more customized second stage of full reset or just a soft reset that concerns the sensor and DAC chips. It also records the MAC address of the tagger-controlling PC for further communication. (This cannot be handled in the Reset_hard stage as all registers on the EC and FPGA are cleared and the PC's MAC address stamped on the hard reset packet (R-packet) cannot be saved) | ||
| − | + | The control packets type bytes leading to states 00X pertaining to these reset modules are: | |
| + | {| class="wikitable" border="1" align="center" style="text-align:center" cellspacing="0" cellpadding="4" | ||
| + | ! colspan="3" | Packet Type Byte || colspan="2" | Effect on the FPGA | ||
| + | |- | ||
| + | ! Type || Hex || Bin || State || Description | ||
| + | |- | ||
| + | | R || 0x52 || 0101 0010 || 000 || align="left" | "Reset_hard" instruction | ||
| + | |- | ||
| + | | "R'" || 0xD2 || '''1'''101 0010 || 001 || align="left" | Essentially an 'R' byte with '1' in the MSB instructing the FPGA to enter a reset cycle of the soft kind. | ||
| + | |} | ||
| + | |||
| + | Both Reset modules yield control to the Transmitter to deliver a status packet to the PC (state 101). | ||
| + | |||
| + | |||
| + | == Programming Details of Rest_hard == | ||
| + | The Reset_hard module is written essentially as a list of module instantiations that perform EC control register read and write operations. The instances are "daisy-chained" to maintain chronological order - a "Done" signal from a preceding module is a "Go" for the following. Occasionally this list of instances is punctuated with counters intended to produce the required wait times and other specialized modules. | ||
| + | |||
| + | Programming the MAC interface requires the use of these specialized modules because the interface has an internal set of 16-bit control registers which are accessed indirectly through the use of general EC control registers. (See manual for more details.) The extra read/write operations necessary to use these indirect registers have been aggregated into ''MACwrToAddr'' in order to make this complication transparent to the higher level modules. These and other modules have in turn been used to create the ''MACaddrLoad'' module, which is responsible for loading the EC's factory-designated MAC address (stored in EC's flash memory) the above-mentioned indirect registers. This module also records a copy of these values in the [[FPGA_Registers#MAC_Register|MAC Address Register]] of the FPGA for the purpose of writing future packets. | ||
| + | |||
| + | Among other special modules, the ''INTcatcher'' is used to listen for "Self-Initialization Complete" interrupt (mask 0100). The Reset_hard block has also been instrumented with a dbShort external signal that "shorts out" the waiting counters for debig purposes. | ||
| + | |||
| + | |||
| + | === Ports === | ||
* ''Clk'': [in] clock | * ''Clk'': [in] clock | ||
| Line 21: | Line 45: | ||
| − | [[FPGA_Registers# | + | [[FPGA_Registers#MAC_Address_Registers|MAC Address Register]] Control Lines |
* ''MACregs_En'': [out] register enable (write) signal | * ''MACregs_En'': [out] register enable (write) signal | ||
* ''MACregs_A'': [out] byte address (4-bit) | * ''MACregs_A'': [out] byte address (4-bit) | ||
| Line 31: | Line 55: | ||
* ''TxRx_Aout'': [out] EC control register address (8-bit) | * ''TxRx_Aout'': [out] EC control register address (8-bit) | ||
* ''TxRx_Dout'': [out] EC control register write value | * ''TxRx_Dout'': [out] EC control register write value | ||
| − | * ''TxRx_RiW'': [out] | + | * ''TxRx_RiW'': [out] active-high read, active-low write flag |
* ''TxRx_Din'': [in] EC control register return value | * ''TxRx_Din'': [in] EC control register return value | ||
* ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]]. | * ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]]. | ||
* ''dbShort'': [in] debug signal to bypass EC reset waiting periods | * ''dbShort'': [in] debug signal to bypass EC reset waiting periods | ||
| + | |||
| + | |||
| + | == Programming Details of Rest_soft == | ||
| + | |||
| + | Reset_soft works like a counter, triggering a "Go" signal for an ''AutoRd'' module instance. A write signal to the [[FPGA_Registers#MAC_Register|MAC Address Register]] is also triggered for the first six bytes (payload bytes three through eight) as these represent the MAC address of the PC. The following two bytes are the Debug Byte and Chip Reset Mask in that order. The reset signals to the DAC and/or the ADC are triggered immediately on the receipt of the Mask Byte. | ||
| + | |||
| + | |||
| + | === Ports === | ||
| + | |||
| + | * ''Clk'': [in] clock | ||
| + | |||
| + | |||
| + | Reset Signals | ||
| + | * ''Rst: [in] asynchronous reset | ||
| + | * ''DAC_iRst'': [out] active-low reset signal for the DAC chip. | ||
| + | * ''SPI_iRst'': [out] active-low reset signal for the SPI bus (i.e. for the ADC) | ||
| + | |||
| + | |||
| + | [[FPGA_Registers#State_Register|State Register]] Control Lines | ||
| + | * ''state_En'': [out] state register enable (write) signal | ||
| + | * ''state_D'': [out] (3-bit) state register input | ||
| + | * ''state_Q'': [in] (3-bit) state register output | ||
| + | |||
| + | |||
| + | [[FPGA_Registers#MAC_Register|MAC Address Register]] Control Lines | ||
| + | * ''MACregs_En'': [out] register enable (write) signal | ||
| + | * ''MACregs_A'': [out] byte address (4-bit) | ||
| + | * ''MACregs_D'': [out] 8-bit input value | ||
| + | |||
| + | |||
| + | * ''DBbyte'': [out] latched output bus that holds eight debug bits specified in the R' packet from PC. As of the time of writing this documentation, no use for these have been found. | ||
| + | |||
| + | |||
| + | [[FPGA_Transceiver|Transceiver]] Control Lines | ||
| + | * ''TxRx_Go'': [out] "Go" signal to read/write an EC control register byte | ||
| + | * ''TxRx_Aout'': [out] EC control register address (8-bit) | ||
| + | * ''TxRx_Dout'': [out] EC control register write value | ||
| + | * ''TxRx_RiW'': [out] active-high read, active-low write flag | ||
| + | * ''TxRx_Din'': [in] EC control register return value | ||
| + | * ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]]. | ||
Latest revision as of 19:57, 20 October 2009
- See also Programming the Ethernet Controller for a survey of modules and a general discussion of FPGA design approach.
(00X) Reset Modules
The reset modules Reset_hard (000) and Reset_soft (001) coordinate various stages of the board reset. The former, analogous to the cold boot of a computer, performs the basic initial reset steps dealing mainly with the startup and configuration of the Ethernet Controller chip (EC). The latter module is a more customized second stage of full reset or just a soft reset that concerns the sensor and DAC chips. It also records the MAC address of the tagger-controlling PC for further communication. (This cannot be handled in the Reset_hard stage as all registers on the EC and FPGA are cleared and the PC's MAC address stamped on the hard reset packet (R-packet) cannot be saved)
The control packets type bytes leading to states 00X pertaining to these reset modules are:
| Packet Type Byte | Effect on the FPGA | |||
|---|---|---|---|---|
| Type | Hex | Bin | State | Description |
| R | 0x52 | 0101 0010 | 000 | "Reset_hard" instruction |
| "R'" | 0xD2 | 1101 0010 | 001 | Essentially an 'R' byte with '1' in the MSB instructing the FPGA to enter a reset cycle of the soft kind. |
Both Reset modules yield control to the Transmitter to deliver a status packet to the PC (state 101).
Programming Details of Rest_hard
The Reset_hard module is written essentially as a list of module instantiations that perform EC control register read and write operations. The instances are "daisy-chained" to maintain chronological order - a "Done" signal from a preceding module is a "Go" for the following. Occasionally this list of instances is punctuated with counters intended to produce the required wait times and other specialized modules.
Programming the MAC interface requires the use of these specialized modules because the interface has an internal set of 16-bit control registers which are accessed indirectly through the use of general EC control registers. (See manual for more details.) The extra read/write operations necessary to use these indirect registers have been aggregated into MACwrToAddr in order to make this complication transparent to the higher level modules. These and other modules have in turn been used to create the MACaddrLoad module, which is responsible for loading the EC's factory-designated MAC address (stored in EC's flash memory) the above-mentioned indirect registers. This module also records a copy of these values in the MAC Address Register of the FPGA for the purpose of writing future packets.
Among other special modules, the INTcatcher is used to listen for "Self-Initialization Complete" interrupt (mask 0100). The Reset_hard block has also been instrumented with a dbShort external signal that "shorts out" the waiting counters for debig purposes.
Ports
- Clk: [in] clock
Reset Signals
- Rst: [in] asynchronous reset
- Eth_iRst: [inout] EC active-low reset pin
- Eth_iINT: [in] EC active-low interrupt signal
State Register Control Lines
- state_En: [out] state register enable (write) signal
- state_D: [out] (3-bit) state register input
- state_Q: [in] (3-bit) state register output
MAC Address Register Control Lines
- MACregs_En: [out] register enable (write) signal
- MACregs_A: [out] byte address (4-bit)
- MACregs_D: [out] 8-bit input value
Transceiver Control Lines
- TxRx_Go: [out] "Go" signal to read/write an EC control register byte
- TxRx_Aout: [out] EC control register address (8-bit)
- TxRx_Dout: [out] EC control register write value
- TxRx_RiW: [out] active-high read, active-low write flag
- TxRx_Din: [in] EC control register return value
- TxRx_Done: [in] "Done" signal from Transceiver.
- dbShort: [in] debug signal to bypass EC reset waiting periods
Programming Details of Rest_soft
Reset_soft works like a counter, triggering a "Go" signal for an AutoRd module instance. A write signal to the MAC Address Register is also triggered for the first six bytes (payload bytes three through eight) as these represent the MAC address of the PC. The following two bytes are the Debug Byte and Chip Reset Mask in that order. The reset signals to the DAC and/or the ADC are triggered immediately on the receipt of the Mask Byte.
Ports
- Clk: [in] clock
Reset Signals
- Rst: [in] asynchronous reset
- DAC_iRst: [out] active-low reset signal for the DAC chip.
- SPI_iRst: [out] active-low reset signal for the SPI bus (i.e. for the ADC)
State Register Control Lines
- state_En: [out] state register enable (write) signal
- state_D: [out] (3-bit) state register input
- state_Q: [in] (3-bit) state register output
MAC Address Register Control Lines
- MACregs_En: [out] register enable (write) signal
- MACregs_A: [out] byte address (4-bit)
- MACregs_D: [out] 8-bit input value
- DBbyte: [out] latched output bus that holds eight debug bits specified in the R' packet from PC. As of the time of writing this documentation, no use for these have been found.
Transceiver Control Lines
- TxRx_Go: [out] "Go" signal to read/write an EC control register byte
- TxRx_Aout: [out] EC control register address (8-bit)
- TxRx_Dout: [out] EC control register write value
- TxRx_RiW: [out] active-high read, active-low write flag
- TxRx_Din: [in] EC control register return value
- TxRx_Done: [in] "Done" signal from Transceiver.