FPGA Idler

(010) Idle

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs

• Clk: clock
• /Rst: asynchronous, active-low reset
• state_in: 3-bit state value

• TxRx_D: 8-bit data from transceiver
• TxRx_Done: pulse from transceiver to signal transfer complete
• TxRx_Go: transceiver go line
• TxRx_R/W: read/write flag for transceiver
• TxRx_Aout: register address bus for transceiver

blocks

• Request INT0RD (0x76) register via reqFromAddr pulsed by the LoopEn signal from Looper (below).
• Looper
  • Switch to determine if this state should loop on itself or continue to the next state.
  • inputs
    • S_En: state enable
    • TxRx_Done: Done pulse from transceiver
    • TxRx_Data: D_out bus from transceiver
  • outputs
    • LoopEn: pulse to repeat fetch cycle; Loop <= S_En and TxRx_Done and TxRx_Data(6)
    • Done: pulse to finish state; connects to state counter as an enable; Done <= S_En and TxRx_Done and not TxRx_Data(6)
    • New_St: new state value to load into state register; goes to 011 when Done is high