FPGA Idler
Revision as of 00:14, 3 June 2008 by Senderovich (talk | contribs)
- See also Programming the Ethernet Controller for a survey of modules and general discussion of FPGA design approach.
(010) Idler
The Idler Block corresponding to state 010 continuously is the default module running an "idle process". It awaits an interrupt corresponding to "Receive FIFO non-empty", unpon which it transitions to state 011 - Read.
Programming Details
The Idler is essentially a state-conscious wrapper around an INTCatcher module instatiation to which the interrupt mask "1000" is passed (selecting the "Rx FIFO non-empty" interrupt as opposed to "Self-Initialization Complete" etc.) INTCatcher only returns a "Done" pulse when the requested interrupt was found so the change of state to "Read" (011) is set to trigger on this "Done" signal.
Ports
- Clk: [in] clock
- Rst: [in] asynchronous reset
- Eth_iINT: [in] EC interrupt pin
- state_in: [in] 3-bit FPGA state value
Transceiver Control Lines
- TxRx_Din: [in] EC control register return value
- TxRx_Done: [in] "Done" signal from Transceiver.
- TxRx_Go: [out] "Go" signal to read an EC control register byte
- TxRX_RiW: [out] active-high read, active-low write flag
- TxRx_Aout: [out] EC control register address (8-bit)