FPGA Transmitter

(1X1) Transmitter

The Transmitter is responsible for compiling report packets for sending to the PC. As discussed elsewhere, the output packets from the digital boards come in "S" and "D" varieties corresponding to "status" - data from sensor chips, and "DAC values" respectively. The selection between these packet types is articulated via the middle bit of the state value: 101 corresponds to S-packet and 111 corresponds to D-packet. After composing the packet and ordering its transmission via the interface with the Ethernet Controller chip (EC), the module yields control to the Idler to await the next request from the PC.

Programming Details of Rest_hard

The natural design approach for this dual-purpose block (sending two very different packets) is to perform the general preparations for transmission including the transmissions buffer pointer settings and packet header composition and then pass control to one of the two child modules that append the appropriate data to the packet depending on the packet type. As such, the Transmitter is enabled when the state value bits 2 and 0 are high and in due course pulses its child modules, DPAcket and SPacket with a "Go" signal selected by the state bit 1.

The major complication in our approach to packet composition is the limited auto-write (easy sequential write) interface of the transmission buffer of the CP220X chips. Upon a transmission failure the auto-write interface is disabled, forcing the controller to switch to random access mode. We resolved, in our design, to just use the latter approach. This mode requires setting the 16-bit buffer address pointer and then writing the desired 8-bit value. Thus, every byte required three write operations. These operations have been aggregated into the RAwrToAddr (Random Access WRite TO ADDRess) module to abstract this complication from the higher-level Transmitter block. One feature of this modules is that it remembers the address of the last byte written and can be told to advance by itself to the next address by writing '1' to the MSB of its address bus. The caveat to using this feature is that the module must only be instantiated once and its control lines must be passed to the children. In this way, the simplicity of the auto-write interface is, in some sense, restored.

Ports

• Clk: [in] clock

Reset Signals

• Rst: [in] asynchronous reset

(111) Transmit "D"

This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.

inputs

• Clk: clock
• /Rst: asynchronous, active-low reset
• State: 3-bit state value

internal signals

• S_En: state enable, S_En <= not (St(2) or St(1) or St(0))
• Go: when S_En goes high Go pulses for one cycle

blocks

• Loader
  • Loads the DAC values into a packet in the transmission buffer of the CP2200/1. Loops through all values and loads them in order (channel zero to channel thirty-one).
  • inputs
    • Clk: clock
    • /Rst: asynchronous, active-low reset
    • Go: pulse to begin loading a packet
    • TxRx_Done: Done signal on transceiver
    • Data: 14-bit data bus from internal registers
  • outputs
    • TxRx_Go: Go signal on transceiver
    • TxRx_RW: R/W signal on transceiver
    • TxRx_A: A_in bus on transceiver
    • TxRx_D: D_in bus on transceiver
    • Done: pulse to signal completion
• Sender
  • Tells CP2200/1 to send the packet
  • inputs
    • Clk: clock
    • /Rst: asynchronous, active-low reset
    • Go: pulse to begin, connected to Done signal from Loader
    • TxRx_Done: Done signal from transceiver
  • outputs
    • TxRx_Go: Go signal on transceiver
    • TxRx_RW: R/W signal on transceiver
    • TxRx_A: A_in bus on transceiver
    • TxRx_D: D_in bus on transceiver
    • Done: pulse to signal completion
    • New_St: 3-bit bus of new state to write to state register; goes to 010 when Done is high